Maia 300: Microsoft promises gigawatt-scale deployment of its own inference chip from 2027
Microsoft launched its third generation of in-house AI chips, the Maia 300, on Monday, October 12, 2026, at the OCP Global Summit in San Jose. The company says the chip is intended as the primary inference system for Microsoft's products and services, with production rollout from 2027 and plans for multigigawatt deployments of the Maia family. Readers should, however, distinguish between the concrete specifications and the company's own efficiency figures, which cannot yet be independently verified.
The news: a third-generation Maia
The Maia 300 follows in the footsteps of the Maia 100 and Maia 200, and according to The Verge the chip is designed to be the "primary AI inference system" for Microsoft's products and services. The company highlights that it should improve the cost and efficiency of running AI workloads in the cloud, and that it is better suited to the latest reasoning models and agent-based tasks (The Verge) (ea73348c).
The rollout to production begins in 2027, according to both The Verge and Notebookcheck (81bb6821). The chip was unveiled at the OCP Global Summit 2026 in San Jose on Monday, and according to Yahoo Finance it will form part of what the company calls multigigawatt deployments beginning "next year" (Yahoo Finance) (2e309c50). Microsoft promises further details at the Ignite conference in November (6eb2bfd1).
The hardware: chiplet design with a 2 nm compute die
Technically, the Maia 300 is built as a package of multiple chiplets. The main compute portion is manufactured with TSMC's advanced N2P process at 2 nanometers, while separate memory and I/O chiplets are included in the package. This architecture allows Microsoft to manufacture different components with process nodes tailored to their respective needs (Notebookcheck) (81bb6821).
The stated figures place the chip in the top tier of today's AI accelerators:
- 13.8 PFLOPS FP4 and 6.9 PFLOPS FP8 of compute power
- 288 GB HBM4 across eight stacks, with 18 TB/s of memory bandwidth
- 3.2 TB/s of bidirectional scale-up bandwidth
- 950 W maximum power for the entire SoC
TechPowerUp additionally states that the package contains four DDR RDIMM memory tiles as system-level main memory — a detail that does not appear in Notebookcheck's specification overview and should therefore be read with some caution (TechPowerUp) (48b8642a).
At the system level, the design scales to 96 accelerators per rack — a "Maia Pod" — and up to around 12,000 accelerators in a scale-up domain (81bb6821, 48b8642a).
Scale and place in Microsoft's fleet
The Maia 200 is already in production use: It runs Microsoft Copilot in the US, Europe and Australia, and according to The Decoder, GitHub Copilot and Foundry will follow by the end of the year (6eb2bfd1). CEO Satya Nadella has, according to the same source, described the effort as "our biggest bet yet on our own silicon" (6eb2bfd1).
Scott Guthrie, executive vice president of Microsoft's cloud group, framed the plans this way, as reported by The Verge: "We will scale our Azure Maia family to multigigawatt deployments from 2027, making Maia the primary AI inference system for Microsoft's products and services" (ea73348c).
Reuters has additionally reported, cited by Mobile World Live, that Microsoft potentially plans to deploy more than one million Maia 300 chips "next year" (Mobile World Live) (e8ef2975). This figure has not been confirmed by a primary document, and its relationship to the 2027 production timeline is unclear — "next year" may refer to 2027, but the sources do not allow this to be established.
The efficiency claims: believe it, but don't verify it
This is where the distinctions between fact and marketing matter most. Guthrie says, according to The Verge: "We expect Maia 300 to deliver 40 percent more tokens per megawatt compared to leading GPU-based systems. And in a full 96-accelerator configuration, it delivers up to 7 times rack-scale token throughput compared to Maia 200" (ea73348c).
These are thus company statements, not independently verified facts. Notebookcheck points to the crux of the problem: Microsoft "has not provided sufficient details about the competing GPU configurations to independently determine the extent of the efficiency advantage" (81bb6821). Without knowing which GPUs, in which configuration, and under which workloads the comparison is made, the 40 percent figure cannot be checked.
There is also an unresolved internal inconsistency in the coverage: TechPowerUp refers to "70 percent more tokens per Watt" for the Maia 200, while The Decoder and Yahoo Finance cite 1.7x tokens per watt in Teams. This may be the same figure presented differently, but the cited sources do not resolve this — it should be left open (48b8642a, 6eb2bfd1, 2e309c50).
Market reaction and significance
The market reacted measurably to the news: Nvidia fell 1.5 percent and AMD 3.4 percent on the day, according to Barron's via MSN (MSN/Barron's) (8b394cc5). Rishi Jaluria, an analyst at RBC Capital Markets, framed it as vertical integration that could improve Azure AI unit economics (8b394cc5).
It is worth keeping the basis for the stock market movements precise: This concerns a single day's movement, not a lasting trend in the chip market.
What remains to be seen
Several central questions remain open:
- TSMC N2P at volume — the 2 nm process is new, and whether Microsoft can secure sufficient manufacturing capacity at multigigawatt scale in 2027 is unresolved.
- Independent benchmark figures — no third party has yet measured the Maia 300's performance or efficiency.
- Pricing — no pricing information is available.
- The alignment of the timelines — whether more than one million chips can actually be deployed "next year," and how that relates to the 2027 production start, is unclear.
- More details promised at Ignite in November — several of the specifications and claims may then be either clarified or better illuminated.
For now, the safe footing is this: Microsoft has published a technical specification with concrete hardware — a 2 nm compute die in a chiplet design, 288 GB HBM4 at 18 TB/s, 13.8 PFLOPS FP4, and 950 W — and an ambition for its own silicon to carry the bulk of the company's AI inference from 2027. The efficiency figures, on the other hand, remain the company's own account.

