OpenAI, Broadcom, AMD and Samsung on the bottleneck: It's power, not the transistor
When top executives from OpenAI, Broadcom, AMD and Samsung shared a stage in front of more than 150 semiconductor industry leaders, none of them disputed the premise moderator Patrick Moorhead opened with: the transistor is no longer the constraint on AI silicon. Power, memory bandwidth and packaging are now what set the limits — and that shapes everything from OpenAI's first in-house chip, Jalapeño, to Broadcom's projection of 5–10 gigawatt campuses by 2031.
At the closing panel of the Global Semiconductor Alliance's U.S. Executive Forum in Menlo Park, California, on September 22, 2026, four of the industry's most important chip decision-makers gave their version of what that means in practice. The reporting is based on the panel moderator Moorhead's own account, published in Forbes and updated October 2, 2026.
The premise no one disputed
Moorhead, a senior contributor at Forbes and founder of the analyst firm Moor Insights & Strategy, opened the panel with the claim that the transistor is no longer the bottleneck for AI silicon — power, memory bandwidth and packaging are.
On stage were Paul Cho, president of Samsung Semiconductor; Mark Papermaster, CTO of AMD; Charlie Kawwas, president of Broadcom Semiconductor Solutions Group; and Richard Ho, vice president of hardware at OpenAI. According to Moorhead, none of them disputed the premise — a notable degree of agreement, given that the four companies represent different parts of the value chain: memory, CPUs, specialized accelerators, and an AI developer now building its own silicon.
OpenAI: optimize intelligence per watt
Richard Ho explained why OpenAI is building its own chip at all. Power is the limiting factor, he argued, and a chip aimed at a known set of workloads can be optimized across models, software and silicon to deliver the most intelligence per watt.
He was also clear that OpenAI's chip is intended as a complement to — not a replacement for — commercial GPUs. And he laid out the purchasing logic: OpenAI's purchasing unit is neither a chip nor a rack. It is the entire fleet across multiple campuses, with power allocated by workload. It is a way of thinking that makes power a managed, scarce resource at the top level, not a technical detail.
The foundation is already in place. OpenAI and Broadcom announced a 10-gigawatt collaboration in October 2025, and in June 2026 the two unveiled Jalapeño, OpenAI's first chip — which, according to the reporting, went from initial design to tape-out, meaning handoff to production, in nine months. Both points are company statements relayed by Moorhead; they are not independently verified.
Broadcom: from one gigawatt to 5–10 campuses
Charlie Kawwas delivered the most concrete numbers on the scale of AI training. One gigawatt to train a cluster is no longer enough, he said — the figure is now two to four gigawatts. And he expected a single campus of five to ten gigawatts by 2031.
It is a projection with consequences beyond chip design: facilities at that scale require access to grid power on the order of large power plants, making energy supply and grid connection part of semiconductor planning. This is Kawwas's projection as stated at the panel, not a verified industry observation.
AMD: moving data eats the power
Mark Papermaster pointed to the mechanism behind the power problem: most of the power goes to moving data, not to the computations themselves. That is why AMD moved to chiplets and three-dimensional stacking, he said, and it is why he now describes thermal management and cooling as "job one."
For a supplier of general-purpose processors, the answer is flexibility designed in from the start, he explained. That is why AMD ships Venice CPUs in six variants, one of which targets agentic AI — a reflection of the fact that different AI workloads place different demands on memory, power and cooling.
Samsung: the memory that could reshuffle the deck
Paul Cho answered the question of which constraint could upend the industry by 2031: memory. He delivered, according to Moorhead, the best line of the evening: "Memory used to be one chapter in the textbook of computer architecture, and by 2031 it will be the first page of every design."
The point is that memory bandwidth — how quickly data can be moved to and from the processors — increasingly determines what kinds of systems can be built at all, and that memory therefore must be considered in the design from the first page, not as an afterthought. Cho was the only panelist to single out one constraint as potentially industry-upending by 2031.
What the reporting rests on — and its limits
All information about the panel comes from a single account: moderator Patrick Moorhead's own Forbes column. Every statement from the executives is relayed or paraphrased by him, and the two copies available online are the same article in syndication, not independent confirmation.
Moorhead himself discloses that AMD, Broadcom and Samsung are clients of his firm Moor Insights & Strategy — as are Nvidia and Qualcomm. That means he has business relationships with three of the four companies on stage, something readers should weigh in how the conversation is framed.
The company claims — Broadcom's gigawatt projections, OpenAI's nine months from design to tape-out for Jalapeño, the Venice variants — are likewise the companies' own assertions relayed through a columnist, not independently verified facts.
Why this is worth noting
Even with those caveats, the panel points to a consistent shift: chip development used to be about shrinking transistors and packing in more of them. Now it is about making power, data movement and cooling add up — at facilities that, by the industry's own leaders' account, may require multiple gigawatts each.
The numbers framing the next five years are concrete: two to four gigawatts per training cluster today, according to Kawwas; campuses of five to ten gigawatts by 2031; memory as the "first page" of every design that same year; and a first OpenAI chip that took nine months from design to the start of production, within a 10-gigawatt collaboration with Broadcom. If all those numbers hold, decisions about AI chips will increasingly be made at the energy and system level — not the transistor level.